The Mountain View, Calif. company’s report, “The Cost of Poor Software Quality in the US,” finds that software quality issues may have cost the U.S. economy more than $2.4 trillion this year as the software industry is building up what the company calls a historic number of deficiencies.

The report, sponsored by Synopsys and produced by the Consortium for Information & Software Quality (CISQ), finds that cybercrime is a leading cause of these issues, with losses due to cybercrime rising 64% between 2020 and 2021, with 2022 on track for another 42% increase.

According to the report, cybercrime is predicted to cost the world $7 trillion in 2022, and the average cost of a data breach in the U.S. is now $9.44 million, up from $9.05 million the year prior.

In fact, the quantity and cost of cybercrime incidents have been on the rise for over a decade, and now account for a sum equivalent to the world’s third largest economy after the U.S. and China, the report found.

The software supply issues continues to be a major IT problem and are getting worse, with the report finding that the number of failures due to weaknesses in open-source software components accelerated by 650% from 2020 to 2021.

With problems with underlying third-party components rising significantly, Synopsys and CISQ urge the importance of responsible and comprehensive open-source security and risk management. The report of course highlights high-profile incidents, including the Log4Shell vulnerability which surfaced last year and is still causing problems for organizations.

However, the CISQ and Synopsys report identified technical debt as the largest obstacle for organizations to overcome. Technical debt, the cost of rework in software development and accumulated deficiencies that are time-consuming and expensive to fix, is leaving systems and organizations vulnerable, the report says.

Due to these issues, the technical debt in the U.S. has risen to more than $1.5 trillion this year, the report found.

Herb Krasner, the report’s author and a retired professor of software engineering at the University of Texas, Austin, says the report offers proactive advice for engineers, project teams and organizational leaders to improve the quality of the software the use and build.

“Now is the time to turn our attention to recent developments and emerging solutions to help improve the poor software quality situation as it now exists and stabilize and reduce the growth rate of CPSQ in the near future,” Krasner says.

Meanwhile, Dr. Anita D’Amico, the Synopsys Software Integrity Group vice president of cross-portfolio solutions and strategy and CISQ Board Member, urges the IT industry to adopt software bills of materials (SBOM) to help give organizations a comprehensive inventory of components used to make a piece of software.

“That means when a new vulnerability is identified in an existing component, organizations can quickly identify where it is in their software and take action to remedy it,” D’Amico says.

The post Software Inefficiencies are Costing U.S. Economy Trillions, Study Says appeared first on My TechDecisions.

Optimized 3nm process achieves 45% reduced power usage, 23% improved performance, and 16% smaller surface area compared to 5nm process

SEOUL, South Korea–(BUSINESS WIRE)–Samsung Electronics Co., Ltd., the world leader in semiconductor technology, today announced that it has started initial production of its 3-nanometer (nm) process node applying Gate-All-Around (GAA) transistor architecture.

Multi-Bridge-Channel FET (MBCFET), Samsung’s GAA technology implemented for the first time ever, defies the performance limitations of FinFET, improving power efficiency by reducing the supply voltage level, while also enhancing performance by increasing drive current capability.

Samsung is starting the first application of the nanosheet transistor with semiconductor chips for high performance, low power computing applications and plans to expand to mobile processors.

“Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as the foundry industry’s first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world’s first 3nm process with the MBCFET,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. “We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology.”

Design-Technology Optimization for Maximized PPA

Samsung’s proprietary technology utilizes nanosheets with wider channels, which allow higher performance and greater energy efficiency compared to GAA technologies using nanowires with narrower channels. Utilizing the 3nm GAA technology, Samsung will be able to adjust the channel width of the nanosheet in order to optimize power usage and performance to meet various customer needs.

In addition, the design flexibility of GAA is highly advantageous for Design Technology Co-Optimization (DTCO)[1], which helps boost Power, Performance, Area (PPA) benefits. Compared to 5nm process, the first-generation 3nm process can reduce power consumption by up to 45%, improve performance by 23%, and reduce area by 16% compared to 5nm, while the second-generation 3nm process is to reduce power consumption by up to 50%, improve performance by 30%, and reduce area by 35%.

Providing 3nm Design Infrastructure & Services with SAFE Partners

As technology nodes get smaller and chip performance needs grow greater, IC designers face challenges of handling tremendous amounts of data to verify complex products with more functions and tighter scaling. To meet such demands, Samsung strives to provide a more stable design environment to help reduce the time required for design, verification and sign-off process, while also boosting product reliability.

Since the third quarter of 2021, Samsung Electronics has been providing proven design infrastructure through extensive preparation with Samsung Advanced Foundry Ecosystem (SAFE) partners including Ansys, Cadence, Siemens, and Synopsys, to help customers perfect their product in a reduced period of time.

[1] For more information on Design Technology Co-Optimization (DTCO), please see below links:

Find the optimal for the best. Part 1

https://semiconductor.samsung.com/us/newsroom/tech-blog/gaa-dtco-for-ppa/

Find the optimal for the best. Part 2

https://semiconductor.samsung.com/us/newsroom/tech-blog/gaa-dtco-for-ppa-part-2/

About Samsung Electronics Co., Ltd.

Samsung inspires the world and shapes the future with transformative ideas and technologies. The company is redefining the worlds of TVs, smartphones, wearable devices, tablets, digital appliances, network systems, and memory, system LSI, foundry and LED solutions. For the latest news, please visit the Samsung Newsroom at http://news.samsung.com.

Quotes from SAFE Partners

• Ansys, [John Lee, Vice President and General Manager of the Electronics, Semiconductor & Optics Business Unit at Ansys]

  “Together, Ansys and Samsung continue to deliver enabling technology for the most advanced designs, now at 3nm with GAA technology. The signoff fidelity of our Ansys multiphysics simulation platform is testament to our continued partnership with Samsung Foundry at the leading edge. Ansys remains committed to delivering the best design experience for our mutual advanced customers.”

• Cadence, [Tom Beckley, Senior Vice President and General Manager, Custom IC & PCB Group at Cadence]

  “We congratulate Samsung on this 3nm GAA production release milestone. Cadence worked closely with Samsung Foundry to enable customers to achieve optimal power, performance, and area for this node using our digital solutions from library characterization to full digital flow implementation and signoff, all driven by our Cadence Cerebrus AI-based technology to maximize productivity. With our custom solutions, we collaborated with Samsung to enable and validate a full AMS flow to enhance productivity from circuit design and simulation through automated layout. We look forward to continuing this collaboration to achieve more tapeout successes.”

• Siemens EDA, [Joe Sawicki, Executive Vice President for the IC-EDA segment of Siemens Digital Industries Software]

  “Siemens EDA is pleased to have collaborated with Samsung to help ensure that our existing software platforms also work on Samsung’s new 3-nanometer process node since the initial development phase. Our longtime partnership with Samsung through the SAFE program generates significant value for our mutual customers, by certification of Siemens industry-leading EDA tools at 3nm.”

• Synopsys, [Shankar Krishnamoorthy, General Manager and Corporate Staff for the Silicon Realization Group at Synopsys]

  “Through our long-standing, strategic collaboration with Samsung Foundry, we are enabling our solutions to support Samsung’s advanced processes, helping our mutual customers significantly accelerate their design cycles. Our support for Samsung’s 3nm process with GAA architecture continues expanding, now with our Synopsys Digital Design, Analog Design and IP products, enabling customers to deliver differentiated SoCs for key high-performance computing applications.”

Contacts

Lisa Warren-Plungy

Samsung Semiconductor, Inc.

Lisa.plungy@samsung.com

The post Samsung Begins Chip Production Using 3nm Process Technology with GAA Architecture appeared first on My TechDecisions.

Engineers from industry to academia recognized for contributions to EDA

SAN FRANCISCO–(BUSINESS WIRE)–#59thDAC–The collective success of the electronics industry has been built on a foundation of individual achievements, with each innovation standing on the shoulders of previous breakthroughs. Much of this has emerged at the annual Design Automation Conference, the largest industry event focused on research and technology for the design and the design automation of electronic chips to systems. DAC and its sponsors – the Association for Computing Machinery (ACM), and the Institute of Electrical and Electronics Engineers (IEEE) – are pleased to announce the four winners of the 2022 Under-40 Innovators Award. The award recognizes the top young innovators who have made a significant impact in the field of design and automation of electronics.

The award winners will be recognized at the 59^th DAC being held July 10 – 14, 2022, at Moscone West in San Francisco, CA. DAC will co-locate with SEMICON West 2022, which is being held at the Moscone Center, North and South Halls, July 12 – 15, 2022. The honorees will participate at the award session being held on Tuesday, July 11 at 8:45 A.M. PDT during the live DAC event.

The 2022 Under-40 Innovation honorees are:

Yanjing Li, University of Chicago

Yanjing Li is an assistant professor in the Department of Computer Science at the University of Chicago. Professor Li’s research interests lie broadly in computer architecture, systems, and very-large-scale integration circuit design. Prior to joining University of Chicago, she was a senior research scientist at Intel Labs. Professor Li received her Ph.D. in electrical engineering from Stanford University. She earned an M.S. in mathematical sciences with honors and a B.S. both in electrical and computer engineering and in computer science from Carnegie Mellon University. She has received various awards, including Google Research Scholar award, Intel Labs Gordy Academy award (highest honor in Intel Labs), and several other Intel recognition awards. She also earned an outstanding dissertation award from the European Design and Automation Association (EDAA) and has received multiple best–paper awards.

Luca Amaru, Synopsys

Luca Amaru is principal R&D engineer in the Silicon Realization Group of Synopsys Inc. He is responsible for designing the next generation of logic optimization and synthesis technologies. Dr. Amaru leads an exceptional team of R&D engineers focusing on logic synthesis. Previously, he was research assistant at EPFL, Integrated Systems Laboratory, Lausanne, Switzerland and visiting researcher at Stanford University. Dr. Amaru received his Ph.D. in computer science from EPFL. He received his double master’s degree in electronic engineering, with honors, from Politecnico di Torino, Turin, Italy, and Politecnico di Milano, Milan, Italy.

Dr. Amaru is author or co-author of over 100 scientific publications, including one book and two book chapters. He has 15 patents and received several awards, including AI 2000 Most Influential Scholar Honorable Mention in Chip Technology, IEEE TCAD Donald O. Pederson Best Paper Award, EDAA Outstanding Dissertation Award and best paper nominations. Dr. Amaru has been part of the organizing committee of the International Workshop on Logic & Synthesis for several years, most recently in quality of General Chair and Program Chair (2019, 2020). He served as Program Co-Chair for the Reed-Muller Workshop in 2019. He has served as technical program committee member for many IEEE/ACM conferences such as DAC, ICCAD, DATE and others. Dr. Amaru is an Associate Editor for IEEE Transactions on CAD. He is a senior member of the IEEE.

Dr. Hesham Omran, Ain Shams University

Dr. Hesham Omran received the B.Sc. (with honors) and M.Sc. degrees from Ain Shams University, Cairo, Egypt, in 2007 and 2010, respectively, and a Ph.D. degree from King Abdullah University of Science and Technology (KAUST), Saudi Arabia, in 2015, all in electrical engineering. From 2008 to 2011, he was a design engineer with Si-Ware Systems (SWS), Cairo, Egypt, where he worked on the circuit and system design of the first miniaturized FT-IR MEMS spectrometer (NeoSpectra), and a research and teaching assistant with the Integrated Circuits Lab (ICL), Ain Shams University. From 2011 to 2016 he was a Researcher with the Sensors Lab, KAUST. He held internships with Bosch Research and Technology Center, CA, USA, and with Mentor Graphics, Cairo, Egypt. In 2016, he rejoined the ICL, Ain Shams University, where he is currently an associate professor. He created the Mastering Microelectronics YouTube channel which has more than 7,000 subscribers. He co-founded Master Micro in 2020 to develop the Analog Designer’s Toolbox (ADT), a novel EDA tool that defines a new paradigm for analog IC design. Dr. Hesham has received several awards including the Egyptian State Encouragement Award for Engineering in 2019. He has published 40+ papers in international journals and conferences. His research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal CAD tools and design automation.

Dr. Guangyu Sun, Peking University

Dr. Guangyu Sun is an associate professor at School of Integrated Circuits in Peking University. He received his B.S. and M.S degrees from Tsinghua University, Beijing, in 2003 and 2006, respectively. He received his Ph.D. degree in Computer Science from the Pennsylvania State University in 2011. His research focuses on design and automation for energy-efficient computer architecture. He has published 150+ journals and refereed conference papers in the area. His work has been recognized with three best paper awards and three best paper nominations. He is a recipient of EDAA outstanding dissertation award, CCF-IEEE CS young computer scientist award, and Beijing Academy of Artificial Intelligence (BAAI) young scientist award. He is a member of CCF, IEEE, and ACM.

DAC offers outstanding training, education, exhibits and networking opportunities for hardware and software designers, researchers, software developers, IT engineers and software tool vendors. Registration for DAC is now open. There are three ways to attend DAC: the complimentary I LOVE DAC pass, Engineering Track pass or Full Conference pass.

The I Love DAC pass is available for the three days of the live event sponsored by Cliosoft, Empyrean Technology and Menta. The I LOVE DAC pass will include:

• Four keynote sessions​ & three SKYtalks
• Tech talks & analyst presentations
• DAC Pavilion Panels
• Engineering Track Poster Sessions
• Design-on-Cloud presentations
• Design on Cloud Hands-on design cloud training
• Access to the DAC exhibition with over 120+ exhibitors
• Daily networking happy hour – Sunday thru Wednesday at the live event

For more information on the DAC program and registration please visit: www.dac.com

About DAC

The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community representing more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area with approximately 160 of the leading and emerging EDA, silicon, intellectual property (IP) and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM’s Special Interest Group on Design Automation (ACM SIGDA).

Design Automation Conference acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

Contacts

Michelle Clancy, 59^th DAC Publicity Chair

Press@dac.com or call 1-503-702-4732

The post Four Exceptional Innovators Selected to Receive the Design Automation Conference Under-40 Innovators Award appeared first on My TechDecisions.

Educational sessions for design engineers, IT professionals and data scientists focusing on AI/ML and Cloud-based design

SAN FRANCISCO–(BUSINESS WIRE)–#59thDAC—The Design Automation Conference (DAC), the premier event devoted to the design and design automation of electronic chips to systems, has enhanced its educational training program for 2022. The popular Thursday is Training Day program provided by Doulos, allows DAC attendees to attend quality design training sessions on trending and sought-after subjects. Complimenting the Thursday is Training Day program, is a new session, Machine Learning Bootcamp for Data Scientists, from Catalit and three training sessions on Tuesday and Wednesday for IT professionals provided by Microsoft Azure, Google and NetApp in the Design-On-Cloud Theater, sponsored by Synopsys.

The 59^th DAC will be held at Moscone West Center in San Francisco, CA, from July 10–14, 2022. DAC will co-locate with SEMICON West 2022, which is being held at Moscone North and South halls.

Thursday is Training Day offers DAC attendees the opportunity to learn a variety of popular programming subjects from leading training provider Doulos. Attendees may choose sessions from two parallel tracks. Many attendees will want to attend both the morning and afternoon sessions from the same track, but it is also possible to mix-and-match sessions from two different tracks or to attend just a single half-day session.

Thursday is Training Day sessions provided by Doulos:

• Track 1, Part I: Moving to Embedded C++
• Track 1, Part II: Anatomy of an Embedded Linux System & User/Kernel Debug

• Track 2, Part I: The Python Language: Become a Pythoneer!
• Track 2, Part II: Deep Learning for Electronic Engineers

In addition to the traditional Thursday is Training Day, Doulos will host a lunch and learn tutorial on Python for Scientific Computing and Deep Learning on Wednesday, July 13, at DAC between 12:15-1:15 p.m. In this lunch and learn session, you will learn enough to start using Python as a scripting language and you will become sufficiently familiar with Python to start making sense of the emerging libraries and frameworks used for deep learning. This tutorial will teach you some of the amazing things you can do with Python right out-of-the-box! Pre-registrants also receive a $50.00 discount coupon to attend one Doulos main sessions on Thursday is Training Day. Lunch and learn registration.

Machine Learning Bootcamp for Data Scientists provided by Catalit

This hands-on machine learning bootcamp is a half-day session where students learn to train machine learning models to solve both regression and classification problems. At the end of attending both modules the students will have learnt how to prepare the data and feed it to a machine learning model and learn the most useful concept in machine learning: rapid iteration. Detailed information can be found at: Machine Learning Bootcamp

Module 1: Introduction to machine learning in Python. At the end of this module the students will have learnt how to prepare the data and feed it to a machine learning model, as well as how to evaluate the model accuracy.

Module 2: Improving machine learning models. At the end of this module the students will have learnt a method to successfully apply machine learning to problems in their work.

Design On Cloud Theater – Cloud Based Design Training

These complimentary three-hour training sessions provided by Microsoft Azure, Google and Netapps provide IT professionals with skills necessary to support design on cloud. Session will be held at the Design on Cloud Theater in the DAC exhibit hall. Attendees can gain access to all three training sessions with the free I LOVE DAC pass, an Engineering badge or Full Conference badge.

• Tuesday, July 12 – Hands-on Lab: Build a Hybrid Burst to Cloud environment with NetApp “Design Anywhere” Cloud-Bursting EDA Workloads with Bi-directional Caching of Job Data
• Wednesday, July 13 – How to run EDA tools on the Azure Cloud
• Wednesday July 13 – Interactive Google Cloud Hands-on Workshop

Session details, including summaries, presenter information and room numbers, can be found at: https://www.dac.com/Conference/Hands-On-Training. DAC advanced registration and training session registration is now open.

About DAC

The Design Automation Conference (DAC) is recognized as the premier event for the design and design automation of electronic chips to systems. A diverse worldwide community representing more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. More than 125 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies, and technologies. The conference offers outstanding educational training and networking opportunities for both the academic and industry communities. A highlight of DAC is its exhibition and suite area with approximately 170 of the leading and emerging EDA, intellectual property (IP), AI, Cloud and design services providers. The conference is sponsored by the Association for Computing Machinery’s Special Interest Group on Design Automation (ACM SIGDA), and the Institute of Electrical and Electronics Engineer’s Council on Electronic Design Automation (IEEE CEDA).

Design Automation Conference acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

Contacts

For more information, please contact:

Michelle Clancy: Press@dac.com or call 1-303-530-4334

The post Quality Designer and IT Training at the 59th Design Automation Conference appeared first on My TechDecisions.

DUBLIN–(BUSINESS WIRE)–The “Semiconductor Intellectual Property Global Market Report 2021: COVID-19 Growth and Change” report has been added to ResearchAndMarkets.com’s offering.

The global semiconductor intellectual property (IP) market is expected to grow from $4.60 billion in 2020 to $5.06 billion in 2021 at a compound annual growth rate (CAGR) of 10%. The market is expected to reach $7.02 billion in 2025 at a CAGR of 8.5%.

The semiconductor intellectual property (IP) market consists of sales of semiconductor intellectual property and related services by entities (organizations, sole traders, and partnerships) that provide integrated circuit layout design that is the intellectual property of its creator or party.

Semiconductor IP is a piece of design that is a reusable unit of logic or functionality or a layout of a design that is developed with the idea of licensing it to many vendors for using it as a building block in different chip designs. There is a license fee for its usage or royalty for every device made using that piece of IP.

The main types of design IP in semiconductor intellectual property (IP) are processor IP, interface IP, memory IP, and others. The processor IP offers an intellectual property right for the design of the processor. Processors are typically produced in the form of soft IP and analog blocks. The different IP cores involve softcore, hardcore and include various revenue sources such as royalty, licensing. It is implemented in several sectors such as consumer electronics, telecom, automotive, healthcare, and others.

Asia Pacific was the largest region in the semiconductor intellectual property (IP) market in 2020. North America was the second-largest market in the semiconductor intellectual property market. The regions covered in this report are Asia-Pacific, Western Europe, Eastern Europe, North America, South America, Middle East, and Africa.

New technology launches are a key trend gaining popularity in the semiconductor IP market. Key players in the market are focusing on new technological innovations to maintain a comparative advantage over competitors in the industry. For example, in June 2020, Imagination Technologies, a UK-based semiconductor company, announced the launch of IMG iEW400, the latest IP based on Ensigma Wi-Fi technology.

The iEW400 integrates RF and baseband and is intended for low-power and battery-powered applications such as the internet of things (IoT), wearables, and wearables. Further, in February 2020, Synopsys, a US-based electronic design automation company that focuses on silicon design and verification, silicon intellectual property, and software security and quality announced the launch of a new DesignWare ARC communications IP subsystem for wireless narrowband IoT designs.

The DesignWare ARC IoT Communications IP Subsystem has a low-power ARC EM11D Processor for effective RISC and DSP performance, which is crucial for IoT applications that require low-bandwidth connectivity.

In September 2020, NVIDIA, a US-based semiconductor company acquired Arm Limited from SoftBank Group Corp (SBG) and the SoftBank Vision Fund, for $40 billion. Under this deal, NVIDIA will expand Arm’s IP licensing portfolio with NVIDIA technology. Arm Limited is a UK-based company offering semiconductor IP.

The growing adoption of connected devices is expected to contribute to the growth of the semiconductor IP market in the forecast period. Physical objects that can communicate with one another and other systems over the internet are referred to as connected devices. Internet of Things (IoT) is generally referred to as connected devices.

These are physical objects that connect with other devices through the internet or various ways such as WiFi, NFC, Bluetooth, mobile networks. IoT devices are manufactured using electronics such as semiconductors, microprocessors, and other chips.

According to Norton, a US-based antivirus and anti-malware software developing company estimates that in 2021 there are around 11.6 billion IoT devices used, and it will grow to 21 billion IoT devices by 2025. The growing adoption of connected devices or IoT devices will drive the semiconductor IP market.

Major players in the semiconductor intellectual property market are

• Arm Holdings
• Synopsys
• Cadence Design Systems
• CEVA Inc.
• Imagination Technologies
• eMemory Technology Incorporated
• Rambus
• Mentor Graphics
• Faraday Technology
• Lattice Semiconductor
• Achronix Semiconductor
• Dolphin Integration
• Open-Silicon
• Xilinx
• Sonics Inc.
• Fujitsu
• MediaTek
• VeriSilicon Holdings
• Wave computing
• Silvaco
• Intel

Key Topics Covered:

1. Executive Summary

2. Semiconductor Intellectual Property Market Characteristics

3. Semiconductor Intellectual Property Market Trends and Strategies

4. Impact Of COVID-19 On Semiconductor Intellectual Property

5. Semiconductor Intellectual Property Market Size and Growth

5.1. Global Semiconductor Intellectual Property Historic Market, 2015-2020, $ Billion

5.1.1. Drivers Of the Market

5.1.2. Restraints On the Market

5.2. Global Semiconductor Intellectual Property Forecast Market, 2020-2025F, 2030F, $ Billion

5.2.1. Drivers Of the Market

5.2.2. Restraints On the Market

6. Semiconductor Intellectual Property Market Segmentation

6.1. Global Semiconductor Intellectual Property Market, Segmentation by Design IP, Historic and Forecast, 2015-2020, 2020-2025F, 2030F, $ Billion

• Processor IP
• Interface IP
• Memory IP
• Others

6.2. Global Semiconductor Intellectual Property Market, Segmentation by IP Core, Historic and Forecast, 2015-2020, 2020-2025F, 2030F, $ Billion

• Soft Core
• Hard Core

6.3. Global Semiconductor Intellectual Property Market, Segmentation by Revenue Source, Historic and Forecast, 2015-2020, 2020-2025F, 2030F, $ Billion

• Royalty
• Licensing

6.4. Global Semiconductor Intellectual Property Market, Segmentation by Industry Vertical, Historic and Forecast, 2015-2020, 2020-2025F, 2030F, $ Billion

• Consumer Electronics
• Telecom
• Automotive
• Healthcare
• Others

7. Semiconductor Intellectual Property Market Regional and Country Analysis

7.1. Global Semiconductor Intellectual Property Market, Split by Region, Historic and Forecast, 2015-2020, 2020-2025F, 2030F, $ Billion

7.2. Global Semiconductor Intellectual Property Market, Split by Country, Historic and Forecast, 2015-2020, 2020-2025F, 2030F, $ Billion

For more information about this report visit https://www.researchandmarkets.com/r/ezsquu

Contacts

ResearchAndMarkets.com

Laura Wood, Senior Press Manager

press@researchandmarkets.com

For E.S.T. Office Hours Call 1-917-300-0470

For U.S./CAN Toll Free Call 1-800-526-8630

For GMT Office Hours Call +353-1-416-8900

The post Global Semiconductor Intellectual Property Market Research Report 2021 – ResearchAndMarkets.com appeared first on My TechDecisions.

Two New Divisions to Drive mAI Consulting Services and AI Asset Performance Management Products

SAN JOSE, Calif.–(BUSINESS WIRE)–BISTelligence, a leading supplier of manufacturing AI-based solutions and services for high-tech and industrial manufacturing, launched early last month, is focused on expanding its innovative new asset performance management (APM) solutions for industrial manufacturing through a newly created division, Aidentyx. At the same time, BISTelligence will ramp a new mAI® global consulting services group focused on high-tech and industrial manufacturing.

BISTelligence is a carve out of BISTel, a leading provider of engineering and software automation products to global semiconductor and FPD manufacturers. The semiconductor products group was sold to Synopsys last month. Following the sale to Synopsys, BISTelligence was formed with the creation of two divisions. One focused on manufacturing AI services and one focused on proliferating the adoption of the company’s award-winning AI GrandView APM products suite, targeting the $500B smart manufacturing sector. BISTelligence aims to build on its 21-year-old BISTel legacy of technology innovation, empowering engineers and bringing intelligent, real-time, data analytics software solutions to market that detect, analyze, and predict outcomes to everyday manufacturing problems. The new entity aims to establish itself as a premier digital transformation provider with manufacturing AI services and solutions that exceeds the vision of industry 4.0.

“We are pleased to announce the creation of BISTelligence,” said W.K. Choi, CEO. “BISTelligence’s AI services team will continue to deliver top class services to our high-tech customers. Our new and exciting Aidentyx product division will also be able to champion new digital APM technologies that extend asset life, improve factory operations, and help solve one of industrial manufacturing’s biggest headaches – unscheduled downtime.”

BISTelligence offers a wide range of smart manufacturing APM products and mAI consulting services. These includes AI data collection, fault monitoring, and predictive data analytics solutions and services designed specifically for the industrial manufacturing ecosystem. Through Aidentyx’s APM products and BISTelligence’s mAI services, the company enables customers to increase factory and asset performance connecting people, processes, and equipment to ensure continuous optimization.

BISTelligence is headquartered in Seoul, South Korea with operations in the USA, China, and Japan. 210 employees around the world are focused on delivering leading-edge, data collection, data analytics solutions and consulting services that empowers engineers and generates significant insights that helps to eliminate unscheduled production stoppages caused by machine failures. By integrating the latest cloud, AI and IIoT technologies with these highly differentiated AI applications and mAI services, BISTelligence helps manufacturers achieve continuous optimization of plant and asset operations everywhere. For more information, visit bistelligence.ai.

Contacts

Stewart Chalmers

BISTelligence

+1 818-681-3588

Stewart.chalmers@BISTelligence.ai

The post New BISTelligence Spin-Off Focused on Manufacturing AI Excellence appeared first on My TechDecisions.

R&D Group Director for Synopsys’ Digital Design Group Honored as a Pioneer in Design Automation for Power Management

SAN FRANCISCO–(BUSINESS WIRE)–#58DAC–Renu Mehra, R&D group director for the Digital Design Group at Synopsys, was selected as the 2021 recipient of the Marie R. Pistilli Women in Electronic Design Award, a prestigious annual honor that recognizes individuals who have significantly helped advance women in electronic design. The award is named for the late Marie R. Pistilli, co-founder of DAC, who placed a high value on equality, diversity and acceptance.

Mehra, who heads the Synopsys Design Compiler® R&D team, is an organizational leader and innovator, responsible for many advanced technologies including RTL synthesis and optimization, clock gating, multi-voltage design and power management, as well as congestion, PPA and runtime optimizations. She is a pioneer in design automation for power management and provided one of the early visions for automated solutions in this area. As one of the founding members of the IEEE 1801 working group that created the Unified Power Format, she helped shape what is now the dominant power intent specification format for the semiconductor industry.

Mehra earned a bachelor’s degree in Electrical Engineering from the Indian Institute of Technology, Kanpur, and an M.S. and Ph.D. in Electrical Engineering and Computer Sciences from the University of California, Berkeley. She has several U.S. patents and has published in various international conferences. She was Program Chair and General Chair for the IEEE/ACM International Conference on Low Power Electronics and Design (ISLPED) in 2015 and 2016, respectively; she served on Technical Program Committees of several conferences including ISLPED, DAC and ICCAD; and is on the Executive Committee for DAC and ISLPED. She received the 2020 YWCA Silicon Valley Tribute to Women leadership award and was featured in the Global Semiconductor Association’s Women’s Leadership Initiative in 2021.

“I’m very honored and humbled to receive the prestigious Marie R. Pistilli Women in Electronic Design Award,” said Mehra. “Engineering and technology have been my passion for as long as I can remember. I enjoy sharing this passion with other women and team members because it gives me an opportunity to listen to diverse perspectives, explore, be innovative and strive for excellence.”

The Marie R. Pistilli Women in Electronic Design Award to Renu Mehra will be formally presented at the upcoming hybrid Design Automation Conference, December 5 – 10, 2021 at Moscone West Center in San Francisco, California. For more information on the hybrid DAC program and registration please visit: www.dac.com

About the Marie R. Pistilli Women in Electronic Design Award

Women have made important contributions and strides in the semiconductor industry for over 20 years. To recognize those who have dedicated time and effort toward these achievements, the Design Automation Conference (DAC) Executive Committee presents an annual award to honor an individual who has made significant contributions to help women advance in the field of EDA technology. The award is named for DAC’s former organizer, the late Marie Pistilli, who worked tirelessly to further the advancement of women in engineering. Marie passed away in November 2015, but her memory and her legacy live on through her namesake award.

For a list of previous recipients of the award and to obtain details about how to nominate a candidate for 2022, please visit https://www.dac.com/About/Women-in-Technology-DAC.

Advance registration for hybrid DAC is now open; view the program. Complimentary I LOVE DAC passes are available through October 29, 2021. For more information or to register visit: https://www.dac.com/Attend/Registration.

About DAC

The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community representing more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area with approximately 175 of the leading and emerging EDA, silicon, intellectual property (IP) and design services providers. The conference is sponsored by the Association for Computing Machinery’s Special Interest Group on Design Automation (ACM SIGDA), and the Institute of Electrical and Electronics Engineer’s Council on Electronic Design Automation (IEEE CEDA).

Design Automation Conference acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

Contacts

Michelle Clancy: Press@dac.com or call 1-303-530-4334

The post Renu Mehra Receives Marie R. Pistilli Women in Engineering Achievement Award appeared first on My TechDecisions.

MOUNTAIN VIEW, Calif.–(BUSINESS WIRE)–The Linley Group announced that its Fall Processor Conference will return to the Hyatt Regency Hotel in Santa Clara, California on October 20-21 and will feature live presentations addressing chips and IP cores for AI applications, embedded solutions, data centers, automotive, and edge designs. A virtual event, featuring live-streamed presentations, will follow on October 27-29 and November 3-5.

As participants have come to expect from past Linley events, the Fall 2021 conference will feature high-quality technical content that attendees will be able to participate in via in-person attendance during the physical event or via live-stream from around the globe during the virtual event. Participants at the in-person event will be able to interact with the speakers during Q&A and panel discussions each day, and virtual participants will be able to participate in Q&A and breakout sessions with the daily speakers. The programs feature talks and panel discussions covering a broad range of topics such as:

• High-Performance Processors
• Server Acceleration
• SoC Design
• Edge-AI Processing & Software
• Edge IP
• Low-Power AI
• DSP & IoT
• FPGAs for AI

Featured Keynotes:

Linley Gwennap, principal analyst, The Linley Group, will open the conference with a presentation of the latest trends in AI silicon as the technology moves from the cloud to the edge, and Kushagra Vaid, Partner, Eclipse Ventures, will discuss current market trends and investment themes, providing insights into various hardware categories where venture dollars are being allocated.

“Our Linley Fall Processor Conference program represents the post-Moore’s Law era, with architectural innovation and heterogeneous designs driving ongoing performance gains. Our fall program includes new technology disclosures and product announcements from both startups and established semiconductor and IP vendors,” said Bob Wheeler, principal analyst and conference chairperson. “Following the success of our 2020 virtual conference, we are excited to return to an in-person event for those able to attend, followed by a virtual event reaching our global audience.”

Sponsoring companies include Intel, Flex Logix, Arm, Synopsys, CEVA, Arteris IP, Achronix, BrainChip, Lattice, Cadence, Marvell, SiFive, Coherent Logix, Hailo, EdgeCortix, Alphawave IP, Roviero, Deep AI, Esperanto Technologies, Andes Technology, Expedera, ProteanTecs, Untether AI, Movellus, Qualcomm, Syntiant, GlobalFoundries, Tenstorrent, Quadric, ArchiTek, RISC-V, and TechInsights. The Linley Group offers free admission to qualified registrants who sign up by October 15. For the full conference program, and to register, please visit Linley Fall Conference 2021.

About The Linley Group

The Linley Group is the industry’s leading source for independent technology analysis of semiconductors for a broad range of applications including AI, networking, communications, data center, and embedded. The company provides strategic consulting services, in-depth analytical reports, and conferences focused on advanced technologies for chip and system design. The Linley Group is the publisher of the noted Microprocessor Report, a weekly publication. For insights on recent industry news, subscribe to the company’s free email newsletter: Linley Newsletter.

Contacts

Bob Wheeler

The Linley Group

bobw@linleygroup.com
www.linleygroup.com

The post All Things AI and Beyond Featured at the Linley Fall Processor Conference appeared first on My TechDecisions.

Intel Foundry Services will lead the first phase of the U.S. Department of Defense’s RAMP-C program to establish a domestic commercial foundry infrastructure.

SANTA CLARA, Calif.–(BUSINESS WIRE)–What’s New: The U.S. Department of Defense, through the NSTXL consortium-based S2MARTS OTA, has awarded Intel an agreement to provide commercial foundry services in the first phase of its multi-phase Rapid Assured Microelectronics Prototypes – Commercial (RAMP-C) program. The RAMP-C program was created to facilitate the use of a U.S.-based commercial semiconductor foundry ecosystem to fabricate the assured leading-edge custom and integrated circuits and commercial products required for critical Department of Defense systems. Intel Foundry Services, Intel’s dedicated foundry business launched this year, will lead the work.

“One of the most profound lessons of the past year is the strategic importance of semiconductors, and the value to the United States of having a strong domestic semiconductor industry. Intel is the sole American company both designing and manufacturing logic semiconductors at the leading edge of technology. When we launched Intel Foundry Services earlier this year, we were excited to have the opportunity to make our capabilities available to a wider range of partners, including in the U.S. government, and it is great to see that potential being fulfilled through programs like RAMP-C.”

– Pat Gelsinger, Intel CEO

How It Works: Intel Foundry Services will partner with industry leaders, including IBM, Cadence, Synopsys and others, to support the U.S. government’s needs for designing and manufacturing assured integrated circuits by establishing and demonstrating a semiconductor IP ecosystem to develop and fabricate test chips on Intel 18A, Intel’s most advanced process technology.

“The RAMP-C program will enable both commercial foundry customers and the Department of Defense to take advantage of Intel’s significant investments in leading-edge process technologies,” said Randhir Thakur, Intel Foundry Services president. “Along with our customers and ecosystem partners, including IBM, Cadence, Synopsys and others, we will help bolster the domestic semiconductor supply chain and ensure the United States maintains leadership in both R&D and advanced manufacturing. We look forward to a long-term collaboration with the U.S. government as we deliver RAMP-C program milestones.”

Intel recently announced plans to become a major provider of U.S.-based capacity for foundry customers, including an investment of approximately $20 billion to build two new factories in Arizona. These fabs will provide committed capacity for foundry customers and support expanding requirements for Intel products.

Why It’s Important: The U.S. Department of Defense (DOD) has recently sought to diversify its approach to securing advanced microprocessors by leveraging commercially available technologies developed by U.S. companies. Other than Intel, the majority of U.S.-based chip designers are fabless, which means they design and sell integrated circuits that are fabricated by contract manufacturers called foundries. Today, more than 80 percent of leading-edge manufacturing capacity is concentrated in Asia¹, leaving the DOD with limited onshore access to foundry technology capable of meeting the country’s long-term needs for secure microelectronics. The RAMP-C program was created to facilitate the use of a commercially viable onshore foundry ecosystem that will ensure DOD access to leading-edge technology, while allowing the defense industrial base to leverage the benefits of high-volume semiconductor manufacturing and design infrastructure of commercial partners like Intel.

About the Broader Efforts: The RAMP-C program is part of a larger initiative to strengthen government supply chain security and accelerate U.S. leadership across the full spectrum of integrated circuit design, manufacturing and packaging. In October 2020, DOD launched the RAMP program using the Advanced Commercial Capabilities Project Phase 1 Other Transaction Authority. RAMP advances and demonstrates commercial leading-edge physical “back-end” assured design methods that transform a high-level chip design into the complex, technology-specific polygon form that is required as input for the wafer fabrication process. Intel is a participant in this project.

Last year, DOD also awarded Intel the second phase of its State-of-the-Art Heterogeneous Integration Prototype (SHIP) program. The SHIP program enables the U.S. government to access Intel’s U.S. advanced semiconductor packaging capabilities with the goal of developing new approaches toward measurably secure, heterogeneous integration and test of advanced packaging solutions. SHIP will develop the capability to use advanced commercial technology to package and test the integrated circuits designed in RAMP and fabricated through RAMP-C.

More Context: Manufacturing at Intel News | Intel Wins US Government Advanced Packaging Project | Intel Foundry Services Fact Sheet

About Intel

Intel (Nasdaq: INTC) is an industry leader, creating world-changing technology that enables global progress and enriches lives. Inspired by Moore’s Law, we continuously work to advance the design and manufacturing of semiconductors to help address our customers’ greatest challenges. By embedding intelligence in the cloud, network, edge and every kind of computing device, we unleash the potential of data to transform business and society for the better. To learn more about Intel’s innovations, go to newsroom.intel.com and intel.com.

¹ SEMI World Fab Forecast, December 2020.

Statements in this document that refer to future plans or expectations, including with respect to the RAMP-C program and its anticipated benefits, are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see Intel’s most recent earnings release and SEC filings at intc.com.

© Intel Corporation. Intel, the Intel logo and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.

Contacts

Jason Gorss

1-518-698-7765

jason.gorss@intel.com

The post Intel Wins US Government Project to Develop Leading-Edge Foundry Ecosystem appeared first on My TechDecisions.

ARLINGTON, Va.–(BUSINESS WIRE)–JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD209-5B, Low Power Double Data Rate 5 (LPDDR5). JESD209-5B includes both an update to the LPDDR5 standard that is focused on improving performance, power and flexibility, and a new LPDDR5X standard, which is an optional extension to LPDDR5.

Taken together, LPDDR5 and LPDDR5X are designed to significantly boost memory speed and efficiency for a variety of uses including mobile devices, such as 5G smartphones and artificial intelligence (AI) applications. Developed by JEDEC’s JC-42.6 Subcommittee for Low Power Memories, JESD209-5B is available for download from the JEDEC website.

Key updates to this latest version of LPDDR5 include:

• Speed extension up to 8533 Mbps (versus up to 6400 Mbps in the previous revision)
• Signal Integrity improvements with TX/RX equalization
• Reliability improvements via the new Adaptive Refresh Management feature

The new LPDDR5X component of JESD209-5B is an optional extension intended to offer higher bandwidth and simplified architecture in support of enhanced 5G communication performance, and is designed for applications ranging from automotive to high resolution augmented reality/virtual reality and edge computing using AI.

“As one of the fastest memories in recent memory to move from concept to industry standard, LPDDR5x is not only a turbo-charged pacesetter for the smartphone marketplace,” according to Mian Quddus, JEDEC’s Chairman of the Board of Directors, “but a power-conserving solution that will set the bandwidth bar considerably higher in taking 5G into a wider consumer embrace worldwide.”

Industry Support

Micron Technology: “As a leader in low-power memory, Micron collaborated closely with other JEDEC members to define LPDDR5X, providing the mobile ecosystem a critical advancement in higher bandwidth,” said Osamu Nagashima, Micron senior manager of mobile systems architecture and vice chair of the JEDEC low power memories subcommittee. “LPDDR5X’s higher speed interface will open doors to new 5G and AI use cases, delivering better user experiences across memory-intensive applications such as gaming, photography and streaming media.”

Samsung Electronics: “Samsung has joined with others on JEDEC’s JC-42.6 subcommittee in standardizing one of the most eagerly anticipated memory advancements in quite some time — a mobile memory interface that can provide substantial bandwidth expansion with minimal IP change and without compromising power efficiency,” said Doohee Hwang, principal engineer for mobile DRAM product planning, Samsung Electronics. “In lockstep with JEDEC’s LPDDR5/5X standardization process, Samsung also has been working closely with leading manufacturers to pave the road for the next generation of smartphones, laptops and other mobile computing devices.”

Synopsys: “Our customers are developing systems that require significantly higher performance memory interfaces at lower power to address the massive bandwidth demands of mobile, automotive and edge computing applications,” said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. “As an active member of JEDEC, Synopsys is developing IP with the lowest latency and area for the latest JEDEC standards, including LPDDR5X where we already have early customer adoption.”

About JEDEC

JEDEC is the global leader in the development of standards for the microelectronics industry. Thousands of volunteers representing over 300 member companies work together in more than 100 JEDEC committees and task groups to meet the needs of every segment of the industry, manufacturers and consumers alike. The publications and standards generated by JEDEC committees are accepted throughout the world. All JEDEC standards are available for download from the JEDEC website. For more information, visit https://www.jedec.org/.

Contacts

Emily Desjardins

703-907-7560

emilyd@jedec.org

The post JEDEC Publishes New and Updated Standards for Low Power Memory Devices Used in 5G and AI Applications appeared first on My TechDecisions.